1. Field of the Invention
The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors, and wherein the ECC-bits cannot be accessed directly for a read or write process.
2. Description and Disadvantages of Prior Art
At boot time or during runtime many computer systems of different types and categories—be it high—performant server systems or personal computers or processing units in embedded systems—execute a memory test. This is done, in order to assure a correct operation of the computer memory, which is working closely with the computer's processor. In computing systems such memory is called DRAM (Dynamic Random Access Memory). Some prior art memory test procedures write a data pattern (such as 0h or A5A5A5A5h) (hexadecimal) and its respective complement into the memory. When each bit toggles from one to the other value, then the data section of the memory is free from stuck bit errors. Other test procedures write a different pattern to each memory location, such as the address of that memory location and its complement, and also check if the bit locations toggle from one to the other value. By doing this, such software makes sure that every data bit is toggled and not stuck at 0 or 1.
In addition to the pure data space a memory of a higher quality computer also comprises a relatively small section, in which the above-mentioned Error Correction Code (ECC) is stored and operated, in order to correct single-bit errors and detect multi-errors. Each data pattern is thus associated with an ECC pattern. The ECC memory section covers approximately 10-20% of the overall memory.
A problem is that the ECC section cannot be directly accessed bitwise or bitwise by such memory test procedure software. This is true for nearly all computer systems. In order to test the proper operability of the ECC section the user has to use special test patterns that result in known ECC byte patterns.
Prior art solutions in this area have different implementations to perform such ECC test procedures: for example the Power PC 405 GP application note describes a table of known data patterns and the resulting ECC bytes such that a user can create a 0, FF, so-called walking 0's and walking 1's in the ECC byte. This is a very time-consuming test for software and needs 8-10, minimum 4 read/write cycles for every memory location. Here, the user is not free to choose the test data pattern or to define a test that concurrently initializes the memory with a given data set.
The prior art AMIDiag diagnostic tool contains a chipset-specific memory test with ECC on 440 FX, 440 LX, 440 BX, 450 NX & pro fusion. It is a general PC diagnostics utility for a limited set of implementations and not suited for a fast test at boot time.
Further, the prior art mem-test 86 does not include any special test for ECC-protected memory. The same is true with the prior art ultra-XRAM-stress-test tool. Thus, in the latter tests the ECC section is simply not tested.
Further prior art test procedures, such as MATS+ or GALPAT row aim at finding errors in the memory with the full knowledge about the internal architecture and layout of the memory. They use sophisticated algorithms to check for address/data line shorts, stuck-bits, cross-talk etc. In a system environment these time-consuming tests can be used only if the memory architecture is known. For a user of a memory unit, however, the precise memory architecture is not known, thus such tests are not applicable.